1. Field of the invention
This invention relates generally to the doping of a semiconductor substrate to create conductive junctions and circuits, and more specifically, relates to a method for the creation of ultra-shallow doping junctions using elemental doping.
2. Related Art
As our society has become more technology based, semiconductors have come to play a vital role. Semiconductor wafers with accompanying circuitry are commonly used in the manufacture of such everyday items as televisions, radios, and computers. The process of manufacturing semiconductors (which are commonly called chips) typically consists of more than 100 steps, during which hundreds of copies of an integrated circuit are formed on a single wafer. The wafer is commonly a silicon dioxide (SiO2) substrate with electrically conductive surface circuits patterned upon the substrate. The circuits may be of near microscopic size and thickness.
Semiconductor devices have many and varied applications in electrical engineering. Recent engineering developments have yielded extremely small semiconductor chips containing hundreds of thousands of transistors. These chips have made possible great miniaturization of electronic devices.
One of the more important steps in semiconductor manufacture is doping. Doping is the addition of elements other than silicon to provide conductivity within the circuit. P-N junctions are commonly created to assist circuit conductivity. Silicon has four valance electrons. Atoms with one valance electron less than silicon, such as boron, or one more valance electron than silicon, such as phosphorus, are introduced into an area desired for conductivity. The addition of the elements alters the electrical character of the silicon. An element with one less valance electron than silicon, usually boron, creates a xe2x80x9cpositive holexe2x80x9d, or P-type area, as compared to the silicon substrate. An element having one more valance electron than silicon, usually phosphorus, creates a more negative, or N-type area. Electrical conduction can take place between the N and P areas, altering the electrical character of the silicon. In other words, when the P-type and N-type semiconductor regions are adjacent to each other, the regions form a semiconductor diode, and the region of contact is called a P-N junction. A diode is a two-terminal device that has a higher resistance to electric current in one direction and a lower resistance in the opposite direction. The conductive properties of the P-N junction depends on the direction of the applied voltage, which can, in turn, be used to control the directional nature of the device. Therefore, P-N junctions can be used to direct the electrical current flow in a semiconductor in a specific direction. Series of such junctions are used to make transistors in many semiconductor devices. Such semiconductor devices include, among others, solar cells, lasers, and rectifiers.
More efficient use of semiconductor chips has been developed through what is called complementary metal-oxide semiconductor circuitry, or CMOS circuitry, formed by pairs of P and N channel transistors controlled by a single circuit.
In creating P-N junctions, the ideal is to create junctions that are as shallow as possible. The more shallow a junction can be made, yet still remain effective in conducting electricity, the more efficient will be the conduction of electricity. Conversely, the greater the diffusion of the P-N dopant into the substrate, the lower the efficiency of the conduction of electricity through the semiconductor circuit.
Shallow P+ and N+ junctions are required for future generations of VLSI transistors made on bulk silicon substrates and ultra-thin SOI, for hyperabrupt P+ junctions for Esaki tunnel diodes, for shallow P layers to control the threshold voltage of P-channel MOSFETs, and for making thin silicon layers for compliant substrates by using P+ layers as an etch stop along with a hydrogen ion implant layer splitting approach.
Two principal methods of creating shallow P-N dopant junctions upon the semiconductor surface are ion implantation and heat diffusion. In an ion implantation method, ions of the dopant are fired at the wafer surface and embedded therein. In a heat diffusion method, ions of the dopant are placed upon the surface of the wafer and diffused therein with heat. Ion implantation suffers from the limitation that the ion impacts cause damage to the surrounding silicon matrix. This damage interferes with the efficiency and conductivity of electricity conduction. Heat diffusion has a serious limitation as well. Heat diffusion tends to diffuse the dopant too greatly, reducing conductive efficiency.
Shallow junctions in silicon are commonly made by implanting ions using low implantation energy. Implant energies from 1 KeV to 10 KeV are currently being investigated for forming ultra-shallow junctions. However, impacts from ion implantation still create point defects in the semiconductor lattice that can lead to enhanced diffusion of the dopant atom making it difficult to achieve ultra-shallow junctions. To our knowledge, the shallowest junction made to date using ion implantation are on the order of 30-50 nm deep into the semiconductor.
Some attempts have been made within the art to improve the quality of semiconductor junctions. Prior art of interest in the field of doping semiconductor substrate surfaces includes U.S. Pat. No. 6,037,640 (Lee); U.S. Pat. No. 5,866,472 (Noslehi); U.S. Pat. No. 5,310,711 (Drowley et al.); U.S. Pat. No. 5,256,162 (Drowley et al.); U.S. Pat. No. 5,242,859 (Degelomo et al.); U.S. Pat. No. 5,183,777 (Doki et al.); U.S. Pat. No. 4,951,603 (Yoshino et al.); U.S. Pat. No. 4,804,438 (Rhodes); and U.S. Pat. No. 4,392,453 (Luscher). The Lee patent discloses a method for making junctions by co-implanting a non-dopant at a higher energy and at a greater depth than the dopant ion. The low energy, dopant implantation step is followed by a fast isothermal annealing step. Junctions 10-45 nanometers deep are said to be created. The Noslehi, Drowley et al. (""711 and ""162) and Degelomo et al. patents each disclose thermally activated direct gas phase doping methods. The direct diffusion of the dopant gas creates heavily doped junctions. These gas phase dopant methods are said to have the potential of creating junctions at a depth of 1000 A (100 nm) or less. The Doki et al. patent discloses an implantation method which involves the formation of a dopant containing film on the surface of a silicon substrate. After the formation of the film, which is composed of hydrogen compounded with either boron, phosphorus, or arsenic, the substrate is heated to cause diffusion. This method is said to create junctions at a depth of 1000 A (100 nm) or less. The Yoshino et al., Rhodes, and Luscher patents each involve the use of vacuum systems in the production of semiconductors. The Yoshino et al. patent discloses an apparatus which deposits semiconductor layers on a substrate in a vacuum chamber. The Rhodes patent discloses a method for depositing conductive layers on silicon substrates under vacuum. The Luscher patent discloses a method for producing a semiconductor film through the use of molecular beams which coat the wafer in a vacuum system.
In accordance with the invention, a method is provided for making ultrashallow diffused junctions using an elemental dopant.
The method is comprised of the steps of cleaning a semiconductor wafer so as to provide a clean reaction surface, loading the cleaned wafer onto a stage located in a vacuum system, placing a quantity of elemental dopant atoms in a partially enclosed elemental dopant source located within a secondary vacuum enclosure, depositing a quantity of the elemental dopant atoms having thermal velocities onto the surface of the wafer, heating the wafer so as to diffuse the elemental dopant atoms into the wafer, and removing the wafer from the vacuum system.
Advantageously, the heating comprises heating the wafer in an ultra-high vacuum so as to diffuse the portion of the doping atoms into the wafer.
Preferably, the heating comprises heating the wafer to a temperature of about 700 C. to about 900xc2x0 C.
Preferably, the deposition and heating steps are carried out simultaneously.
Advantageously, the method further comprises the steps of hydrogen terminating the surface of the wafer.
Preferably, the hydrogen termination of the wafer surface is carried out before loading of the wafer into the system is carried out, and removal of the hydrogen is carried out after the wafer is loaded into the system.
Preferably, the terminated hydrogen is removed from the surface of the wafer. Advantageously, the hydrogen-removal is carried out by heating the wafer by using at least one flash lamp to a temperature of at least 450xc2x0 C.
Advantageously, at least part of the surface of the wafer is covered with a layer of photoresist, and the method further comprises the step of removing the photoresist from the wafer after the wafer is removed from the vacuum system and before the wafer is heated.
Preferably, at least one protective layer is deposited on the surface of the wafer. Advantageously, the protective layer is a cap layer consisting of one of silicon, a nitride, and a metal. Preferably, the at least one protective layer comprises two to five layers of an elemental dopant.
Advantageously, a silicide layer is deposited on the surface of the wafer, and the silicide layer is deposited prior to deposition of the elemental dopant on the wafer.
Preferably, the wafer is comprised of a material selected from the group consisting of silicon, GaAs, SiC, and GaN.
Advantageously, the elemental dopant is selected from the group consisting of boron, phosphorus, antimony, indium, aluminum, arsenic, and gallium.
Preferably, the elemental dopant is boron.
Advantageously, the method produces diffused junctions having a depth of up to about 500 nm.
Preferably, the diffused junctions have a depth of up to about 10 nm.
Preferably, the vacuum system is operated at a pressure of between about 10xe2x88x926 torr to about 10xe2x88x9211 torr.
Advantageously, the wafer is maintained at a temperature beneath ambient room temperature during deposition of the elemental dopant.
Preferably, the wafer is maintained at ambient room temperature during deposition of the elemental dopant
Advantageously, the wafer is maintained at a temperature above ambient room temperature during deposition of the elemental dopant.
Preferably, the wafer is maintained at a temperature from about 200xc2x0 C. to about 500xc2x0 C. during deposition of the elemental dopant.
Advantageously, the wafer is maintained at a temperature of less than about 200xc2x0 C. during deposition of the elemental dopant.
Preferably, the method is used to create junctions in a VLSI transistor.
Advantageously, the method is used in a process to create esaki tunnel diodes.
Preferably, the method is used in a process to create P-channel MOSFETs.
Preferably, the method further comprises the steps of implanting a layer of hydrogen ions in a layer within the wafer; and separating the wafer along the hydrogen ion layer using a hydrogen ion layer splitting technique.
Advantageously, the dopant source is heated by a heat source comprising one of a K-cell, an electron beam, and an in source heater.
In accordance with a further aspect of the invention, a method of the invention comprises preparing a surface of a wafer to be doped, and doping the wafer by exposing the reaction surface to an elemental boron dopant so that the boron is deposited on and adheres to the surface and diffuses into the surface so as to produce a doped wafer.
Preferably, the wafer is heated to provide annealing thereof.
Advantageously, the hydrogen termination step comprises the step of removing any native oxide on the surface.
Advantageously, the flashing off of hydrogen is carried out in an ultra high vacuum.
Preferably, the doping step is carried out after the flashing off of the hydrogen.
Preferably, the doping step is carried out with the surface being hydrogen terminated.
Advantageously, the wafer comprises silicon and, after the hydrogen terminator step, the wafer is heated to no more than about 400xc2x0 C., the element boron doping step is carried out, and the wafer is flash heated to 700-900xc2x0 C. to diffuse the boron into the silicon.
The approaches described herein allow the creation of junctions of less than 10 nm thickness without damaging the surrounding silicon.
Other features and advantages of the invention will be set forth in, or will be apparent from, the detailed description of the preferred embodiments which follows.